FIG. 9 is a diagram illustrating the construction of a servo control device in a conventional optical disk apparatus.
In this optical disk apparatus, a reflected light of a laser beam, which faced on the disk recording surface through a field lens 93 installed in an optical pickup 92 and which is emitted, is employed so as to read out data recorded in an optical disk 91. The quantity of light of the reflected light detected by employing a sensor such as a photo detector 94 is converted from analog data to digital data by an A/D converter 95 and is inputted to a digital signal processor 96. While the quantity of light of the reflected light detected varies in amounts that are influenced by the disk rotations, external vibrations, or the like, the quantity of light of the reflected light has to be kept at a large value so as to read out data correctly. To realize the same, it is necessary to perform a focus control and a tracking control.
The focus control is to control the field lens against the surface deflection of the disk so that a distance between the field lens 93 installed in the optical pickup and the disk recording surface should be kept constant and that the disk recording surface should be located within the depth of focus of the laser. The tracking control is one that controls the field lens 93 against decentering of the disk so that the optical spot should scan on the track correctly. The focus control and the tracking control are realized by detecting a focus error signal and a tracking error signal which respectively represent whether or not focusing and tracking are performed correctly from the reflected light, calculating a focus driving amount and a tracking driving amount by digital operations, and driving the field lens 93 by signals passing through D/A converters 97C and 97D, respectively. As servo controls required for the optical disk apparatus, there are a spindle control which controls a spindle motor 98 for rotating the optical disk, a traverse control for driving the optical pickup 92, and the like, other than the focus control and the tracking control.
As a construction of the digital signal processor which performs the servo control in a conventional optical disk apparatus, there is a method disclosed in Japanese Published Patent Application No. Hei. 10-255283, entitled as “A control method of an optical pickup and an optical disk apparatus”. In this prior official report, there is disclosed the construction of a servo system in the optical disk device having a CPU as a main arithmetic device and a DSP as an auxiliary arithmetic device which supplements the CPU, and a system in which various tasks required for the servo control of the optical device are processed in the CPU and the DSP divisionally.
Hereinafter, a conventional digital signal processor which comprises two arithmetic devices and performs a servo control in the optical disk apparatus will be described with reference to FIG. 7.
In FIG. 7, reference numerals 11 and 12 denote arithmetic devices, numeral 13 denotes an external bus, numerals 14 and 16 denote program memory areas, numerals 15 and 17 denote arithmetic logic units “ALU”, numeral 18 denotes a task list, numeral 19 denotes an external start-up factor, numeral 70 denotes a processing pointer A, numeral 21 denotes a program counter, numeral 22 denotes an instruction decoder, numeral 23 denotes a program halt notification signal, numeral 24 denotes a termination status storage register, and numeral 25 denotes a processing demand generation circuit.
The arithmetic device 11 and the arithmetic device 12 are connected each other by the external bus 13, and it is possible that the arithmetic device 11 should refer to the internal register of the arithmetic device 12. The arithmetic device 11 makes the arithmetic logic unit 15 activated by a program stored in the program memory area 14, and calculates driving values required for the spindle control, the traverse control, or the like. Similarly, the arithmetic device 12 also makes the arithmetic logic unit 17 operated by a program stored in the program memory area 16, and calculates driving values needed for the focus control, the tracking control, or the like.
For example, a processing A which is a focus control processing and a processing B which is a tracking control processing in the arithmetic device 12 are previously transferred from the arithmetic device 11 via the external bus 13 and are stored in the program memory area 16. Moreover, starting addresses of the processing A and the processing B are transferred from the arithmetic device 11 to the task list 18 which is established in the arithmetic device 12. The task list 18 stores the starting addresses of respective processings and execution modes of respective processings as a pair, respectively. The execution mode indicates whether the corresponding processing can be performed or not. When a high (hereinafter referred to as “Hi”) pulse is inputted to the external start-up factor 19 which is generated at a constant period, the arithmetic device 12 is initialized so that the processing pointer A 70 should indicate the head of the task list 18. Further, 0 indicating no conclusion is set to the termination status storage device 24. In addition, the arithmetic device 12 copies the address stored in the task list 18 that is indicated by the processing pointer A 70 to the program counter 21. At this time, when the execution mode corresponding to the address indicated by the processing pointer A 70 indicates “0” meaning incapability of execution, the processing pointer is incremented by 1 and tries to copy the address of the following processing to the program counter 21.
According to the above-mentioned operation, the program of the processing A is activated and is read cut from the program memory area 16. Then, when the program of the processing A read out is interpreted by the instruction decoder 22, the arithmetic logic unit 17 is operated to perform the processing A.
When the program counter 21 reaches the termination address of the processing A and the program halt instruction is inputted to the instruction decoder 22, the arithmetic device 12 makes the instruction decoder 22 output the program halt notification signal 23 to the processing pointer A 70. When the program halt notification signal 23 is notified to the processing pointer A 70, the arithmetic device 12 changes the indication destination to the task list 18 from the processing A to the processing B and copies the starting address of the processing B to the program counter 21. Thereby, the program of the processing B is activated to perform the processing B. The arithmetic device 12 repeats similar operations for all processings stored in the task list 18, and sets 1 indicating the conclusion of the processings to the termination status storage register 24 when all the processings are concluded.
The arithmetic device 11 monitors the termination status storage register 24 of the arithmetic device 12, and when 0 indicating that the arithmetic device 12 is not under execution of the processing is set, the arithmetic device 11 can demand the arithmetic device 12 to execute a processing C which is not stored in the task list 18, employing the processing demand generation circuit 25.
According to the so-constructed digital signal processor of the optical disk apparatus, processings can be distributed such that the focus control and the tracking control which require high operating speeds are performed by the arithmetic device 12 while the spindle control and the traverse control which only require a low working speeds are performed by the arithmetic device 11, whereby the arithmetic device 11 can be realized by an inexpensive small sized circuit.
However, according to the construction of the above-described conventional digital signal processor, when the arithmetic device 11 demands that the arithmetic device 12 should execute the processing C, the arithmetic device 11 has to monitor the termination status storage register 24, thereby resulting in a processing waiting time for the processing of the arithmetic device 12 at the arithmetic device 11. For example, as shown in a timing chart in FIG. 8, when the execution demand for the processing C is generated from the arithmetic device 11 while the arithmetic device 12 is performing the processing A, the arithmetic device 11 has to be in a waiting state with monitoring the termination status storage register 24 until the arithmetic device 12 concludes the processing A and the processing B.
Further, the processing C, for which the processing is demanded from the arithmetic device 11, can not be performed after the arithmetic device 12 concluded the processing A and before it starts the processing B.
In addition, it is not possible to perform the processing C, for which the processing is demanded from the arithmetic device 11, with interrupting the processing A which is under execution by the arithmetic device 12.
The present invention is made to solve the above-mentioned problems and has for its object to provide a digital signal processor which can remove the waiting time at the arithmetic device 11 as well as can change the processing order at the arithmetic device 12.